1. Field of the Invention
This invention relates to electronic circuits, and more particularly, to efficiently performing timing characterization of high-speed clocks signals with low-speed input/output pins.
2. Description of the Relevant Art
Manufacturing processing defects and variations increased as the integration of chip functionality has increased. Advances in manufacturing processing allowed chip functionality to increase as geometric dimensions of devices and metal routes on semiconductor chips reduced. The defects and variations may greatly affect the functionality and performance of on-die circuits. The manufacturing defects may cause a given signal route, such as a clock signal, to significantly vary from expected behavior. For example, the clock duty cycle may vary from expected values. Additionally, the clock signal may have an appreciable amount of clock jitter.
During a debug process of a chip design, designers may spend a significant amount of time attempting to find and fix failures. Soft failures from clock cycle variations and appreciable clock jitter may cause both consistent and inconsistent failure patterns. A significant amount of effort and time may be used to determine the root cause of these patterns. Further, a first batch of semiconductor wafers may be processed in a similar time span by the same equipment. Still, the silicon dies in this first batch of wafers may include varying clock signal parameters due to process variations. The clock signal behavior may vary from expected behavior in a common manner due to the similar processing conditions. However, other silicon dies in a second batch of wafers may be processed at another time and/or possibly on other equipment. The clock signal behavior may vary from expected behavior in a different manner from dies in the first batch. Therefore, debugging the chips on the wafers becomes even more difficult.
Further still, reliably characterizing high-speed signals on the chips may utilize dedicated high-speed input/output (I/O) pins, such as general-purpose I/O (GPIO) pins. However, these types of pins are expensive. Additionally, adding more GPIO pins may not be possible with a fixed pinout of a die package.
In view of the above, methods and mechanisms for efficiently performing timing characterization of high-speed clocks signals with low-speed input/output pins are desired.